Integrating formal verification and high-level processor pipeline synthesis.
Eriko NurvitadhiJames C. HoeTimothy KamShih-Lien LuPublished in: SASP (2011)
Keyphrases
- formal verification
- high level
- functional verification
- model checking
- low level
- automated verification
- model checker
- bounded model checking
- symbolic model checking
- parallel architecture
- pipeline architecture
- parallel processing
- program slicing
- programming language
- distributed memory
- temporal logic
- program synthesis
- higher level
- hardware implementation
- low level features
- processing pipeline
- high speed
- artificial intelligence