Reetuparna Das

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 50

Top Topics

Arithmetic Operations

Benchmark Suite

Top Venues

Publications

Reetuparna Das, Satish Narayanasamy
Systems Challenges and Opportunities for Genomics. Computer 57 (8) (2024)
Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Timothy Dunn, David T. Blaauw, Reetuparna Das, Satish Narayanasamy
nPoRe: n-polymer realigner for improved pileup-based variant calling. BMC Bioinform. 24 (1) (2023)
Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. ISCA (2023)
Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das
Vector-Processing for Mobile Devices: Benchmark and Analysis. IISWC (2023)
Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das
Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. IEEE Trans. Computers 72 (6) (2023)
Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das
Vector-Processing for Mobile Devices: Benchmark and Analysis. CoRR (2023)
Vidushi Goyal, Reetuparna Das, Valeria Bertacco
Hardware-friendly User-specific Machine Learning for Edge Devices. ACM Trans. Embed. Comput. Syst. 21 (5) (2022)
Daichi Fujiki, Alireza Khadem, Scott A. Mahlke, Reetuparna Das
Multi-Layer In-Memory Processing. MICRO (2022)
Reetuparna Das
Special Issue on In-Memory Computing. IEEE Micro 42 (1) (2022)
Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM (2021)
Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi Iyer, Li Zhao, Reetuparna Das
Cache Compression with Efficient in-SRAM Data Comparison. NAS (2021)
Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
GenomicsBench: A Benchmark Suite for Genomics. ISPASS (2021)
Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David T. Blaauw, Reetuparna Das
Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees. ISCA (2021)
Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy
SquiggleFilter: An Accelerator for Portable Virus Detection. MICRO (2021)
Vidushi Goyal, Valeria Bertacco, Reetuparna Das
MyML: User-Driven Machine Learning. DAC (2021)
Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. IEEE J. Solid State Circuits 56 (3) (2021)
Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw
A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array. CICC (2020)
Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. IEEE J. Solid State Circuits 55 (1) (2020)
Yujun Qin, Samuel Gonzalez, Kevin Angstadt, Xiaowei Wang, Stephanie Forrest, Reetuparna Das, Kevin Leach, Westley Weimer
MARTINI: Memory Access Traces to Detect Attacks. CCSW@CCS (2020)
Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space. MICRO (2020)
Vidushi Goyal, Xiaowei Wang, Valeria Bertacco, Reetuparna Das
Neksus: An Interconnect for Heterogeneous System-In-Package Architectures. IPDPS (2020)
Vidushi Goyal, Valeria Bertacco, Reetuparna Das
Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. DAC (2020)
Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das
Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. HPCA (2019)
Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Dennis Sylvester, David T. Blaauw, Reetuparna Das, Ravi R. Iyer
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. IEEE Micro 39 (3) (2019)
Daichi Fujiki, Scott A. Mahlke, Reetuparna Das
Duality cache for data parallel acceleration. ISCA (2019)
Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester
A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration. ISSCC (2019)
Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers. ACM Trans. Embed. Comput. Syst. 18 (5s) (2019)
Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy
GenAx: A Genome Sequencing Accelerator. ISCA (2018)
Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. CoRR (2018)
Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. ISCA (2018)
Daichi Fujiki, Scott A. Mahlke, Reetuparna Das
In-Memory Data Parallel Processor. ASPLOS (2018)
Kevin Angstadt, Arun Subramaniyan, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, Reetuparna Das
ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata. MICRO (2018)
Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das
Cache automaton. MICRO (2017)
Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin
Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. HPCA (2017)
Arun Subramaniyan, Reetuparna Das
Parallel Automata Processor. ISCA (2017)
Jiecao Yu, Andrew Lukefahr, David J. Palframan, Ganesh S. Dasika, Reetuparna Das, Scott A. Mahlke
Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism. ISCA (2017)
Reetuparna Das
Blurring the Lines between Memory and Computation. IEEE Micro 37 (6) (2017)
Daichi Fujiki, Scott A. Mahlke, Reetuparna Das
In-memory Data Flow Processor. PACT (2017)
Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David T. Blaauw, Reetuparna Das
Compute Caches. HPCA (2017)
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
Mirage cores: the illusion of many out-of-order cores using in-order hardware. MICRO (2017)
Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das
Cache Automaton: Repurposing Caches for Automata Processing. PACT (2017)
Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin
Exploring specialized near-memory processing for data intensive operations. DATE (2016)
Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, Todd M. Austin
ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. ASPLOS (2016)
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. CoRR (2016)
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
Exploring Fine-Grained Heterogeneity with Composite Cores. IEEE Trans. Computers 65 (2) (2016)
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. Parallel Comput. 54 (2016)
William Arthur, Ben Mehne, Reetuparna Das, Todd M. Austin
Getting in control of your control flow with control-data isolation. CGO (2015)
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
DynaMOS: dynamic schedule migration for heterogeneous cores. MICRO (2015)
William Arthur, Sahil Madeka, Reetuparna Das, Todd M. Austin
Locking down insecure indirection with hardware-based control-data isolation. MICRO (2015)
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
Design and Evaluation of Hierarchical Rings with Deflection Routing. SBAC-PAD (2014)
Ritesh Parikh, Reetuparna Das, Valeria Bertacco
Power-Aware NoCs through Routing and Topology Reconfiguration. DAC (2014)
Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge
Quality-of-Service for a High-Radix Switch. DAC (2014)
Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration. MICRO (2014)
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
Heterogeneous microarchitectures trump voltage scaling for low-power cores. PACT (2014)
Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
VIX: Virtual Input Crossbar for Efficient Switch Allocation. DAC (2014)
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
Trace based phase prediction for tightly-coupled heterogeneous cores. MICRO (2013)
Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge
Scaling towards kilo-core processors with asymmetric high-radix topologies. HPCA (2013)
Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi
Application-to-core mapping policies to reduce memory system interference in multi-core systems. HPCA (2013)
Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski
Catnap: energy proportional multiple network-on-chip. ISCA (2013)
Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. Hot Chips Symposium (2012)
Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi
Application-to-core mapping policies to reduce memory interference in multi-core systems. PACT (2012)
Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. PACT (2012)
Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
Swizzle-Switch Networks for Many-Core Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
Composite Cores: Pushing Heterogeneity Into a Core. MICRO (2012)
Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. DAC (2012)
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. IEEE Micro 31 (1) (2011)
Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71 (5) (2011)
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li
Cost-driven 3D integration with interconnect layers. DAC (2010)
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
Aérgia: exploiting packet latency slack in on-chip networks. ISCA (2010)
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir
A case for integrated processor-cache partitioning in chip multiprocessors. SC (2009)
Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
A case for dynamic frequency tuning in on-chip networks. MICRO (2009)
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
Application-aware prioritization mechanisms for on-chip networks. MICRO (2009)
Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA (2009)
Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA (2008)
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das
Performance and power optimization through data compression in Network-on-Chip architectures. HPCA (2008)
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA (2007)
Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Hot Interconnects (2007)