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Aditya Yanamandra
Publication Activity (10 Years)
Years Active: 2008-2011
Publications (10 Years): 0
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Publications
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Asit K. Mishra
,
Aditya Yanamandra
,
Reetuparna Das
,
Soumya Eachempati
,
Ravi R. Iyer
,
Narayanan Vijaykrishnan
,
Chita R. Das
RAFT: A router architecture with frequency tuning for on-chip networks.
J. Parallel Distributed Comput.
71 (5) (2011)
Aditya Yanamandra
,
Soumya Eachempati
,
Niranjan Soundararajan
,
Vijaykrishnan Narayanan
,
Mary Jane Irwin
,
Ramakrishnan Krishnan
Optimizing power and performance for reliable on-chip networks.
ASP-DAC
(2010)
Chrysostomos Nicopoulos
,
Suresh Srinivasan
,
Aditya Yanamandra
,
Dongkook Park
,
Vijaykrishnan Narayanan
,
Chita R. Das
,
Mary Jane Irwin
On the Effects of Process Variation in Network-on-Chip Architectures.
IEEE Trans. Dependable Secur. Comput.
7 (3) (2010)
Yuan Xie
,
Soumya Eachempati
,
Aditya Yanamandra
,
Vijaykrishnan Narayanan
,
Mary Jane Irwin
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
NANOARCH
(2009)
Aditya Yanamandra
,
Mary Jane Irwin
,
Vijaykrishnan Narayanan
,
Mahmut T. Kandemir
,
Sri Hari Krishna Narayanan
In-Network Caching for Chip Multiprocessors.
HiPEAC
(2009)
Aditya Yanamandra
,
Bryan Cover
,
Padma Raghavan
,
Mary Jane Irwin
,
Mahmut T. Kandemir
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations.
IPDPS
(2008)
Prasanth Mangalagiri
,
Karthik Sarpatwari
,
Aditya Yanamandra
,
Vijaykrishnan Narayanan
,
Yuan Xie
,
Mary Jane Irwin
,
Osama Awadel Karim
A low-power phase change memory based hybrid cache architecture.
ACM Great Lakes Symposium on VLSI
(2008)
Niranjan Soundararajan
,
Aditya Yanamandra
,
Chrysostomos Nicopoulos
,
Narayanan Vijaykrishnan
,
Anand Sivasubramaniam
,
Mary Jane Irwin
Analysis and solutions to issue queue process variation.
DSN
(2008)