A low-power phase change memory based hybrid cache architecture.
Prasanth MangalagiriKarthik SarpatwariAditya YanamandraVijaykrishnan NarayananYuan XieMary Jane IrwinOsama Awadel KarimPublished in: ACM Great Lakes Symposium on VLSI (2008)
Keyphrases
- low power
- vlsi architecture
- power consumption
- high speed
- low cost
- cmos technology
- high power
- single chip
- mixed signal
- low power consumption
- real time
- wireless transmission
- digital signal processing
- logic circuits
- nm technology
- image sensor
- power dissipation
- vlsi circuits
- signal processor
- power reduction
- delay insensitive
- cmos image sensor
- query processing