Asit K. Mishra

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 24

Top Topics

Sparse Principal Component Analysis

Top Venues

Publications

Anup Sarma, Sonali Singh, Huaipan Jiang, Ashutosh Pattnaik, Asit K. Mishra, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Chita R. Das
Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs. CoRR (2021)
Asit K. Mishra, Jorge Albericio Latorre, Jeff Pool, Darko Stosic, Dusan Stosic, Ganesh Venkatesh, Chong Yu, Paulius Micikevicius
Accelerating Sparse Deep Neural Networks. CoRR (2021)
Ashutosh Pattnaik, Xulong Tang, Onur Kayiran, Adwait Jog, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das
Opportunistic computing in GPU architectures. ISCA (2019)
Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM (2018)
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA (2018)
Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR (2018)
Asit K. Mishra, Debbie Marr
Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. ICLR (Poster) (2018)
Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. FPGA (2018)
Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
WRPN: Wide Reduced-Precision Networks. ICLR (Poster) (2018)
Asit K. Mishra, Debbie Marr
WRPN & Apprentice: Methods for Training and Inference using Low-Precision Numerics. CoRR (2018)
Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA (2018)
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL (2018)
Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr
Fine-grained accelerators for sparse machine learning workloads. ASP-DAC (2017)
Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr
WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR (2017)
Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
High performance binary neural networks on the Xeon+FPGA™ platform. FPL (2017)
Supriya Kapur, Asit K. Mishra, Debbie Marr
Low Precision RNNs: Quantizing RNNs Without Losing Accuracy. CoRR (2017)
Asit K. Mishra, Debbie Marr
Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. CoRR (2017)
Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
WRPN: Wide Reduced-Precision Networks. CoRR (2017)
Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. FPT (2016)
Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra
ScalCore: Designing a core for voltage scalability. HPCA (2016)
Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Chita R. Das
Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities. PACT (2016)
Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. FPL (2016)
Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr
Hardware accelerator for analytics of sparse data. DATE (2016)
Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr
A sparse matrix vector multiply accelerator for support vector machine. CASES (2015)
Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. HPCA (2014)
Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das
Orchestrated scheduling and prefetching for GPGPUs. ISCA (2013)
Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu
Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA (2013)
Asit K. Mishra, Onur Mutlu, Chita R. Das
A heterogeneous multiple network-on-chip design: an application-aware approach. DAC (2013)
Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance. ASPLOS (2013)
Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das
Application-aware prefetch prioritization in on-chip networks. PACT (2012)
Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
PEPON: performance-aware hierarchical power budgeting for NoC based multicores. PACT (2012)
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC (2012)
Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (2011)
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
A case for heterogeneous on-chip interconnects for CMPs. ISCA (2011)
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar R. Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das
ACCESS: Smart scheduling for asymmetric cache CMPs. HPCA (2011)
Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. DAC (2011)
Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut T. Kandemir, Chita R. Das
METE: meeting end-to-end QoS in multicores through system-wide resource management. SIGMETRICS (2011)
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA (2011)
Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71 (5) (2011)
Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. SC (2010)
Asit K. Mishra, Joseph L. Hellerstein, Walfredo Cirne, Chita R. Das
Towards characterizing cloud backend workloads: insights from Google compute clusters. SIGMETRICS Perform. Evaluation Rev. 37 (4) (2010)
Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
Coordinated power management of voltage islands in CMPs. SIGMETRICS (2010)
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir
A case for integrated processor-cache partitioning in chip multiprocessors. SC (2009)
Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
A case for dynamic frequency tuning in on-chip networks. MICRO (2009)
Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA (2009)
Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA (2008)
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das
Performance and power optimization through data compression in Network-on-Chip architectures. HPCA (2008)
Asit K. Mishra, Aurobinda Routray, Ashok Kumar Pradhan
Detection of Arcing in Low Voltage Distribution Systems. ICIIS (2008)