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Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.
Reetuparna Das
Soumya Eachempati
Asit K. Mishra
Narayanan Vijaykrishnan
Chita R. Das
Published in:
HPCA (2009)
Keyphrases
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high speed
engineering design
circuit design
single chip
low cost
design process
real time
user interface
power dissipation
evaluation model
chip design
low power consumption
formative evaluation
vlsi implementation
physical design
evaluation method
information systems