Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.
Adwait JogAsit K. MishraCong XuYuan XieVijaykrishnan NarayananRavishankar R. IyerChita R. DasPublished in: DAC (2012)
Keyphrases
- memory access
- shared memory
- caching scheme
- main memory
- cache misses
- cache hit ratio
- data access
- access latency
- prefetching
- memory hierarchy
- random access memory
- memory management
- message passing
- access patterns
- high volume
- external memory
- parallel computing
- processing units
- database management systems
- hit ratio
- query processing