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Performance and power optimization through data compression in Network-on-Chip architectures.

Reetuparna DasAsit K. MishraChrysostomos NicopoulosDongkook ParkVijaykrishnan NarayananRavishankar R. IyerMazin S. YousifChita R. Das
Published in: HPCA (2008)
Keyphrases
  • data compression
  • network on chip
  • data reduction
  • compression algorithm
  • compression ratio
  • power consumption
  • compressed data
  • power dissipation
  • database systems
  • high speed
  • interconnection networks
  • network simulator