Aravind Dasu

Publication Activity (10 Years)

Years Active: 2001-2021
Publications (10 Years): 13

Top Topics

Data Representation

General Purpose

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu, Derek Chiou
Specializing FGPU for Persistent Deep Learning. ACM Trans. Reconfigurable Technol. Syst. 14 (2) (2021)
Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou
DO-GPU: Domain Optimizable Soft GPUs. FPL (2021)
Tian Tan, Eriko Nurvitadhi, Aravind Dasu, Martin Langhammer, Derek Chiou
FlexScore: Quantifying Flexibility. IEEE Comput. Archit. Lett. 20 (1) (2021)
Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD (2020)
Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM (2019)
Sanmukh R. Kuppannagari, Rachit Rajat, Rajgopal Kannan, Aravind Dasu, Viktor K. Prasanna
IP Cores for Graph Kernels on FPGAs. HPEC (2019)
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL (2019)
Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA (2019)
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR (2019)
Rui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu
Specializing FGPU for Persistent Deep Learning. FPL (2019)
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA (2018)
Leandro de Souza Rosa, Aravind Dasu, Pedro C. Diniz, Vanderlei Bonato
A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA. J. Signal Process. Syst. 90 (3) (2018)
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL (2018)
Peter Gadfort, Aravind Dasu, Ali Akoglu, Yoon Kah Leow, Michael Fritze
A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM. SoCC (2014)
Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker
Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). Int. J. Reconfigurable Comput. 2011 (2011)
Arvind Sudarsanam, Robert Collier Barnes, J. Carver, Ramachandra Kallam, Aravind Dasu
Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms. IET Comput. Digit. Tech. 4 (2) (2010)
Adarsha Sreeramareddy, Ramachandra Kallam, Aravind Dasu, Ali Akoglu
Self-configurable architecture for reusable systems with Accelerated Relocation Circuit (SCARS-ARC). IPDPS Workshops (2010)
Shant Chandrakar, Abraham Clements, Arvind Sudarsanam, Aravind Dasu
Memory architecture template for Fast Block Matching algorithms on FPGAs. IPDPS Workshops (2010)
Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu
Welcome message. IPDPS Workshops (2010)
Harikrishna Samala, Aravind Dasu
Methodology to derive resource aware context adaptable architectures for FPGAs. IET Comput. Digit. Tech. 4 (1) (2010)
Arvind Sudarsanam, Aravind Dasu, Karthik Vaithianathan
Analysis and Design of a Context Adaptable SAD/MSE Architecture. Int. J. Reconfigurable Comput. 2009 (2009)
Jonathan Phillips, Arvind Sudarsanam, Harikrishna Samala, Ramachandra Kallam, J. Carver, Aravind Dasu
Methodology to derive context adaptable architectures for FPGAs. IET Comput. Digit. Tech. 3 (1) (2009)
Arvind Sudarsanam, Ramachandra Kallam, Aravind Dasu
PRR-PRR Dynamic Relocation. IEEE Comput. Archit. Lett. 8 (2) (2009)
Robert Collier Barnes, Aravind Dasu
Hardware/Software Co-designed Extended Kalman Filter on an FPGA. ERSA (2008)
Thomas Hauser, Aravind Dasu, Arvind Sudarsanam, Seth Young
Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system. Scalable Comput. Pract. Exp. 8 (4) (2007)
Jonathan Phillips, Matthew Areno, Chris Rogers, Aravind Dasu, Brandon Eames
A Reconfigurable Load Balancing Architecture for Molecular Dynamics. IPDPS (2007)
Seth Young, Arvind Sudarsanam, Aravind Dasu, Thomas Hauser
Memory support design for LU decomposition on the starbridge hyper-computer. FPT (2006)
Arvind Sudarsanam, Aravind Dasu
A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations. FPT (2005)
Aravind Dasu, Arvind Sudarsanam
High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications. IPDPS (2005)
Arvind Sudarsanam, Aravind Dasu, Sethuraman Panchanathan
Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures. ERSA (2004)
Ali Akoglu, Aravind Dasu, Sethuraman Panchanathan
Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications. ERSA (2004)
Aravind Dasu, Sethuraman Panchanathan
A wavelet-based sprite codec. IEEE Trans. Circuits Syst. Video Technol. 14 (2) (2004)
Aravind Dasu, Ali Akoglu, Sethuraman Panchanathan
An Analysis Tool Set for Reconfigurable Media Processing. Engineering of Reconfigurable Systems and Algorithms (2003)
Aravind Dasu, Sethuraman Panchanathan
A survey of media processing approaches. IEEE Trans. Circuits Syst. Video Technol. 12 (8) (2002)
Aravind Dasu, Sethuraman Panchanathan
Reconfigurable media processing. Parallel Comput. 28 (7-8) (2002)
Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan
Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing. IPDPS (2002)
Aravind Dasu, Sethuraman Panchanathan
Reconfigurable Media Processing. ITCC (2001)
Aravind Dasu, Sethuraman Panchanathan
Lifting kernel-based sprite codec. VCIP (2001)