MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
Dongkook ParkSoumya EachempatiReetuparna DasAsit K. MishraYuan XieNarayanan VijaykrishnanChita R. DasPublished in: ISCA (2008)
Keyphrases
- multi layered
- network on chip
- high speed
- low cost
- neural learning
- vlsi implementation
- routing algorithm
- power dissipation
- analog vlsi
- management system
- design methodology
- high density
- real time
- physical design
- end to end
- cmos technology
- low power
- multi processor
- host computer
- packet switching
- multithreading
- data flow
- mixed signal
- chip design
- power consumption