Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.
Asit K. MishraXiangyu DongGuangyu SunYuan XieNarayanan VijaykrishnanChita R. DasPublished in: ISCA (2011)
Keyphrases
- memory access
- shared memory
- random access memory
- power dissipation
- data access
- main memory
- input output
- cmos technology
- message passing
- parallel algorithm
- parallel computing
- access patterns
- instruction set
- processing units
- analog vlsi
- lower cost
- memory management
- power consumption
- fiber optic
- low power
- cache misses
- location prediction
- multithreading
- vlsi design
- circuit design
- single chip
- external memory
- low cost
- mobile environments
- parallel processing
- operating system