Somnath Paul

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 27

Top Topics

Graph Transformation

Gate Dielectrics

Eigendecomposition

Spiking Neural Networks

Top Venues

Discret. Math. Algorithms Appl.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. ISCA (2023)
Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
GenomicsBench: A Benchmark Suite for Genomics. ISPASS (2021)
Abdollah Alhevaz, Maryam Baghipur, Ebrahim Hashemi, Somnath Paul
On the sum of the distance signless Laplacian eigenvalues of a graph and some inequalities involving them. Discret. Math. Algorithms Appl. 12 (1) (2020)
Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, R. Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, C. Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits (2020)
Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits (2020)
Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54 (1) (2019)
Somnath Paul
The spectra of a new join of graphs. Discret. Math. Algorithms Appl. 10 (6) (2018)
Bruno U. Pedroni, Sadique Sheik, Hesham Mostafa, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. BioCAS (2018)
Somnath Paul
Conjugate Laplacian matrices of a graph. Discret. Math. Algorithms Appl. 10 (6) (2018)
Abdollah Alhevaz, Maryam Baghipur, Somnath Paul
On the distance signless Laplacian spectral radius and the distance signless Laplacian energy of graphs. Discret. Math. Algorithms Appl. 10 (3) (2018)
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC (2018)
Dongyeob Shin, Jongsun Park, Jangwon Park, Somnath Paul, Swarup Bhunia
Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Des. Test 34 (6) (2017)
Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection. CoRR (2017)
Georgios Detorakis, Sadique Sheik, Charles Augustine, Somnath Paul, Bruno U. Pedroni, Nikil D. Dutt, Jeffrey L. Krichmar, Gert Cauwenberghs, Emre Neftci
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. CoRR (2017)
Robert Karam, Somnath Paul, Ruchir Puri, Swarup Bhunia
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications. ACM J. Emerg. Technol. Comput. Syst. 13 (3) (2017)
Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
Event-driven random backpropagation: Enabling neuromorphic deep learning machines. ISCAS (2017)
Wenchao Qian, Christopher Babecki, Robert Karam, Somnath Paul, Swarup Bhunia
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De
Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE J. Solid State Circuits 52 (4) (2017)
Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity. CoRR (2016)
Somnath Paul
On distance and distance Laplacian spectra of corona of two graphs. Discret. Math. Algorithms Appl. 8 (1) (2016)
Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. BioCAS (2016)
Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. CoRR (2016)
Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. BioCAS (2016)
Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. VLSI Circuits (2016)
Christopher Babecki, Wenchao Qian, Somnath Paul, Robert Karam, Swarup Bhunia
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications. IEEE Trans. Computers 65 (10) (2016)
Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci
Synaptic sampling in hardware spiking neural networks. ISCAS (2016)
Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay
Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (1) (2015)
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
Robust low-power reconfigurable computing with a variation-aware preferential design approach. ICICDT (2014)
Milan Nath, Somnath Paul
A note on the Distance spectral radius of some graphs. Discret. Math. Algorithms Appl. 6 (1) (2014)
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri
Energy-efficient hardware acceleration through computing in the memory. DATE (2014)
Milan Nath, Somnath Paul
On the Minimal Distance spectral radius in the Class of bicyclic graphs. Discret. Math. Algorithms Appl. 6 (1) (2014)
Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. IEEE Trans. Computers 62 (11) (2013)
Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia
Reconfigurable ECC for adaptive protection of memory. MWSCAS (2013)
Milan Nath, Somnath Paul
Graph Transformation and Distance spectral radius. Discret. Math. Algorithms Appl. 5 (3) (2013)
Somnath Paul, Abhijit Dana, Soumya Pandit
Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. VDAT (2013)
Lei Wang, Somnath Paul, Swarup Bhunia
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. VLSI Design (2012)
Somnath Paul
On the Maximal Distance spectral radius in a Class of bicyclic Graphs. Discret. Math. Algorithms Appl. 4 (4) (2012)
Anandaroop Ghosh, Somnath Paul, Swarup Bhunia
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. VLSI Design (2012)
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3) (2011)
Somnath Paul, Swarup Bhunia
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). FPGA (2011)
Somnath Paul, Swarup Bhunia
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Xinmu Wang, Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing. NANOARCH (2011)
Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Trans. Computers 60 (1) (2011)
Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST (2010)
Somnath Paul, Hamid Mahmoodi, Swarup Bhunia
calibration at multiple operating points using delay-sensitivity-based path selection. ACM Trans. Design Autom. Electr. Syst. 15 (2) (2010)
Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Swarup Bhunia
System level self-healing for parametric yield and reliability improvement under power bound. AHS (2010)
Somnath Paul, Swarup Bhunia
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. ISLPED (2010)
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. ICCAD (2009)
Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia
MERO: A Statistical Approach for Hardware Trojan Detection. CHES (2009)
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
A variation-aware preferential design approach for memory based reconfigurable computing. ICCAD (2009)
Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. IET Comput. Digit. Tech. 3 (6) (2009)
Somnath Paul, Swarup Bhunia
Computing with nanoscale memory: Model and architecture. NANOARCH (2009)
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. ICCAD (2008)
Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
Collective computing based on swarm intelligence. DAC (2008)
Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. VLSI Design (2008)
Somnath Paul, Swarup Bhunia
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ASP-DAC (2008)
Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
On-Demand Transparency for Improving Hardware Trojan Detectability. HOST (2008)
Yu Zhou, Somnath Paul, Swarup Bhunia
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. DATE (2008)
Yu Zhou, Somnath Paul, Swarup Bhunia
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. ISQED (2008)
Somnath Paul, Swarup Bhunia
Reconfigurable computing using content addressable memory for improved performance and resource usage. DAC (2008)
Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. IOLTS (2007)
Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. ISQED (2007)
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD (2007)
Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. VTS (2007)
Somnath Paul, Swarup Bhunia
Memory based computation using embedded cache for processor yield and reliability improvement. ICCD (2007)
Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta
Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. VLSI Design (1998)