Pascal Meinerzhagen

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 11

Top Topics

International Symposium

Networked Environment

Metal Oxide Semiconductor

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

VLSI Technology and Circuits

Publications

Axel Jantsch, Swaroop Ghosh, Ümit Y. Ogras, Pascal Meinerzhagen
ISLPED 2023: International Symposium on Low-Power Electronics and Design. IEEE Des. Test 41 (1) (2024)
Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits (2023)
Srikanth Venkat Raman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. ITC (2020)
Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. ESSCIRC (2019)
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC (2018)
Robert Giterman, Adam Teman, Pascal Meinerzhagen
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2016)
Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS (2016)
Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2016)
Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. 21 (4) (2016)
Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ESSCIRC (2013)
Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. NEWCAS (2013)
Muhammad Umer Khalid, Pascal Meinerzhagen, Andreas Burg
Replica bit-line technique for embedded multilevel gain-cell DRAM. NEWCAS (2012)