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Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.
Oskar Andersson
Babak Mohammadi
Pascal Meinerzhagen
Andreas Burg
Joachim Neves Rodrigues
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2016)
Keyphrases
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low voltage
trade off
cmos technology
low power
high speed
leakage current
power line
power consumption
random access memory
parallel processing
design considerations
low cost
silicon on insulator
power management
power dissipation
image restoration
mixed signal