Paolo A. Aseron

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 6

Top Topics

Error Detection

Gate Dielectrics

Top Venues

IEEE J. Solid State Circuits

Publications

Srivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Dileep Kurian, Erika Ramirez Lozano, Satish Yada, Saransh Chhabra, Kamakhya Prasad Sahu, Paolo A. Aseron, Ronald Kalim, Anuradha Srinivasan, Tanay Karnik
Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. ISQED (2022)
Vinayak Honkote, Dileep Kurian, Sriram Muthukumar, Dibyendu Ghosh, Satish Yada, Kartik Jain, Bradley Jackson, Ilya Klotchkov, Mallikarjuna Rao Nimmagadda, Shreela Dattawadkar, Pranjali Deshmukh, Ankit Gupta, Jaykant Timbadiya, Ravi Pali, Karthik Narayanan, Saksham Soni, Saransh Chhabra, Praveen Dhama, N. Sreenivasulu, Jisna Kollikunnel, Sureshbabu Kadavakollu, Vijay Deepak Sivaraj, Paolo A. Aseron, Leonid Azarenkov, Nancy Robinson, Arun Radhakrishnan, Mikhail J. Moiseev, Ganeshram Nandakumar, Akhila Madhukumar, Roman Popov, Kamakhya P. Sahu, Ramesh Peguvandla, Alberto Del Rio Ruiz, Mukesh Bhartiya, Anuradha Srinivasan, Vivek De
A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. ISSCC (2019)
Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC (2018)
Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De
Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE J. Solid State Circuits 52 (4) (2017)
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51 (1) (2016)
Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. VLSI Circuits (2016)
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC (2015)
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar
An IA-32 processor with a wide voltage operating range in 32nm CMOS. Hot Chips Symposium (2012)
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC (2012)
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46 (1) (2011)
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46 (1) (2011)
Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3) (2011)
Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
Resilient microprocessor design for high performance & energy efficiency. ISLPED (2010)
Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC (2010)
Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC (2010)
James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC (2010)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44 (1) (2009)
Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. IEEE J. Solid State Circuits 43 (1) (2008)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC (2008)
Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. ISSCC (2007)