Peter Hazucha

Publication Activity (10 Years)

Years Active: 2000-2009
Publications (10 Years): 0

Publications

Pengfei Li, Lin Xue, Peter Hazucha, Tanay Karnik, Rizwan Bashirullah
A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters. IEEE J. Solid State Circuits 44 (11) (2009)
Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. IEEE J. Solid State Circuits 43 (1) (2008)
Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. ISSCC (2007)
Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik
High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. IEEE J. Solid State Circuits 42 (1) (2007)
Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik
Low Voltage Buffered Bandgap Reference. ISQED (2007)
Saravanan Rajapandian, Kenneth L. Shepard, Peter Hazucha, Tanay Karnik
High-voltage power delivery through charge recycling. IEEE J. Solid State Circuits 41 (6) (2006)
Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik
A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters. ISSCC (2006)
Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner
High-frequency DC-DC conversion : fact or fiction. ISCAS (2006)
Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar
Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits 40 (4) (2005)
Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits 40 (4) (2005)
Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED (2004)
Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
CMOS process. IEEE J. Solid State Circuits 39 (9) (2004)
Tanay Karnik, Peter Hazucha, Jagdish Patel
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. IEEE Trans. Dependable Secur. Comput. 1 (2) (2004)
Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC (2003)
Peter Hazucha, Christer Svensson, Stephen A. Wender
Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process. IEEE J. Solid State Circuits 35 (10) (2000)
Peter Hazucha, Christer Svensson
Optimized test circuits for SER characterization of a manufacturing process. IEEE J. Solid State Circuits 35 (2) (2000)