Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process.
Peter HazuchaTanay KamikSteven WalstraBradley A. BloechelJames W. TschanzJose MaizKrishnamurthy SoumyanathGreg DermerSiva G. NarendraVivek DeShekhar BorkarPublished in: CICC (2003)