Shailendra Jain

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 9

Top Topics

Matlab Simulink

Induction Motor

Finite Element Analysis

Top Venues

J. Circuits Syst. Comput.

Mechatron. Syst. Control.

IEEE Trans. Ind. Electron.

Publications

V. Shirish Murty, Shailendra Jain, Amit Ojha
Development of single linear induction motor for high-speed transit system. Soft Comput. 28 (2) (2024)
V. Shirish Murty, Shailendra Jain, Amit Ojha
Analyzing modeled configuration using finite element analysis for performance prediction of LSRM. Neural Comput. Appl. 34 (23) (2022)
V. Shirish Murty, Shailendra Jain, Amit Ojha
Advancements in Converter Topology and control Strategies for switched Reluctance motors: Recent Contributions. Mechatron. Syst. Control. 49 (2) (2021)
V. Shirish Murty, Shailendra Jain, Amit Ojha
Suitability of linear switched Reluctance motor for Advanced Electric Traction System. Mechatron. Syst. Control. 49 (3) (2021)
Jitendra Tandekar, Amit Ojha, Shailendra Jain
Five-Level Cascaded H-Bridge MLC-Based Shunt Active Power Filter for Active Harmonics Mitigation in Distributed Network. J. Circuits Syst. Comput. 28 (2) (2019)
Sameer Singh, Bhavna Jain, Shailendra Jain
Wavelet based real-time power quality monitoring. CCECE (2016)
Rekha Agrawal, Shailendra Jain
A Review of Some Recently Proposed Topologies for Multilevel DC-AC Conversion. J. Circuits Syst. Comput. 25 (12) (2016)
Pradyumn Chaturvedi, Amit Ojha, Shailendra Jain, Arvind Mittal
Unity power factor controller for neutral point clamped active front end converter with DC voltage balancing. ICIT (2016)
Rekha Agrawal, Shailendra Jain
Suitability of Reduced Part Count Multilevel Inverter Topologies for Grid Interfacing. J. Circuits Syst. Comput. 25 (7) (2016)
Sachin Tiwari, Sushma Gupta, Shailendra Jain, Bhim Singh
Soft Computing Techniques for Static Series Voltage Regulator of Self Excited Induction Generator. J. Circuits Syst. Comput. 24 (2) (2015)
Sriram R. Vangal, Shailendra Jain, Vivek De
A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor. ICICDT (2014)
Pradyumn Chaturvedi, Shailendra Jain, Pramod Agarwal
Carrier-Based Neutral Point Potential Regulator With Reduced Switching Losses for Three-Level Diode-Clamped Inverter. IEEE Trans. Ind. Electron. 61 (2) (2014)
Krishna Kumar Gupta, Shailendra Jain
A Novel Multilevel Inverter Based on Switched DC Sources. IEEE Trans. Ind. Electron. 61 (7) (2014)
Lalit Kumar, Krishna Kumar Gupta, Shailendra Jain
Power electronic interface for vehicular electrification. ISIE (2013)
Lalit Kumar, Krishna Kumar Gupta, Shailendra Jain
Architecture and configuration of electrified vehicles: A review. ISIE (2013)
Surhud Khare, Shailendra Jain
Prospects of Near-Threshold Voltage Design for Green Computing. VLSI Design (2013)
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Sriram R. Vangal
IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS. IEEE Micro 33 (2) (2013)
Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. VLSI Design (2012)
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar
An IA-32 processor with a wide voltage operating range in 32nm CMOS. Hot Chips Symposium (2012)
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC (2012)
Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. IEEE J. Solid State Circuits 46 (4) (2011)
Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46 (1) (2011)
Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC (2010)
Julie Ward, Bin Zhang, Shailendra Jain, Chris Fry, Thomas Olavson, Holger Mishal, Jason Amaral, Dirk Beyer, Ann Brecht, Brian Cargille, Russ Chadinha, Kathy Chou, Gavin DeNyse, Qi Feng, Cookie Padovani, Sesh Raj, Kurt Sunderbruch, Robert Endre Tarjan, Krishna Venkatraman, Joseph Woods, Jing Zhou
HP Transforms Product Portfolio Management with Operations Research. Interfaces 40 (1) (2010)
Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. VLSI Design (2010)
Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Hoskote, Nitin Borkar, Shekhar Borkar
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits 43 (1) (2008)
Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. ISSCC (2007)
Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard
Testing High-Speed IO Links Using On-Die Circuitry. VLSI Design (2006)
Shailendra Jain, Pramod Agarwal, H. O. Gupta
A Dedicated Microcontroller based Fuzzy Controlled Shunt Active Power Filter. Intell. Autom. Soft Comput. 11 (1) (2005)
Shailendra Jain, M. Eric Johnson, Fereydoon Safai
Implementing Setup Optimization on the Shop Floor. Oper. Res. 44 (6) (1996)