Matthias Gries

ORCID

Publication Activity (10 Years)

Years Active: 2000-2015
Publications (10 Years): 0

Top Venues

IEEE Trans. Computers

ETH Zurich, Zürich, Switzerland (PHD)

Education History

ETH Zurich, Zürich, Switzerland

PHD

Publications

Benedikt Dietrich, Dip Goswami, Samarjit Chakraborty, Apratim Guha, Matthias Gries
Time Series Characterization of Gaming Workload for Runtime Power Management. IEEE Trans. Computers 64 (1) (2015)
Nikolas Ioannou, Michael Kauschke, Matthias Gries, Marcelo Cintra
Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer. PACT (2011)
Matthias Gries, Ulrich Hoffmann, Michael Konow, Michael Riepen
SCC: A Flexible Architecture for Many-Core Platform Research. Comput. Sci. Eng. 13 (6) (2011)
Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46 (1) (2011)
Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC (2010)
Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. ACM Great Lakes Symposium on VLSI (2010)
Benedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty, Matthias Gries
LMS-based low-complexity game workload prediction for DVFS. ICCD (2010)
Hans-Peter Loeb, Matthias Gries, Christian Sauer
Implementing a Software-Based 802.11 MAC on a Customized Platform. CCNC (2009)
Christian Sauer, Matthias Gries, Hans-Peter Löb
SystemClick: a domain-specific framework for early exploration using functional performance models. DAC (2008)
Sören Sonntag, Matthias Gries, Christian Sauer
SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC. Des. Autom. Embed. Syst. 11 (2-3) (2007)
Christian Sauer, Matthias Gries, Sebastian Dirk
Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform. DATE (2007)
Sören Sonntag, Matthias Gries, Christian Sauer
Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing Networks. Annual Simulation Symposium (2006)
Christian Sauer, Matthias Gries, Jörg-Christian Niemann, Mario Porrmann, Michael Thies
Application-Driven Development of Concurrent Packet Processing Platforms. PARELEC (2006)
Christian Sauer, Matthias Gries, Sören Sonntag, Dietmar Toelle, Bo Wu, Rudi Knorr
Trends in Access Networks and their Implementation in DSLAMs. LCN (2005)
Christian Sauer, Matthias Gries, Sören Sonntag
Modular Reference Implementation of an IP-DSLAM. ISCC (2005)
Sören Sonntag, Matthias Gries, Christian Sauer
Performance Evaluation of VLSI platforms using SystemQ. GI Jahrestagung (1) (2005)
Sören Sonntag, Matthias Gries, Christian Sauer
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC. SAMOS (2005)
Christian Sauer, Matthias Gries, Sören Sonntag
Modular domain-specific implementation and exploration framework for embedded software platforms. DAC (2005)
Hans-Martin Blüthgen, Christian Sauer, Dominik Langen, Matthias Gries, Wolfgang Raab
Application-Driven Design of Cost-Efficient Communications Platforms. GI Jahrestagung (1) (2005)
Matthias Gries
Methods for evaluating and covering the design space during early design development. Integr. 38 (2) (2004)
Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer
Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. CODES+ISSS (2004)
Christian Sauer, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer
Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. PARELEC (2004)
Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
Programming challenges in network processor deployment. CASES (2003)
Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. DATE (2003)
Samarjit Chakraborty, Matthias Gries, Lothar Thiele
Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic. IEEE Real Time Technology and Applications Symposium (2002)
Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli
A framework for evaluating design tradeoffs in packet processing architectures. DAC (2002)
Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Alexander Maxiaguine, Jonas Greutert
Embedded Software in Network Processors - Models and Algorithms. EMSOFT (2001)
Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
FunState-an internal design representation for codesign. IEEE Trans. Very Large Scale Integr. Syst. 9 (4) (2001)
Matthias Gries
The Impact of Recent DRAM Architectures on Embedded Systems Performance. EUROMICRO (2000)

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Publication Activity (10 Years)

Top Topics

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Matthias Gries