A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
Jason HowardSaurabh DigheSriram R. VangalGregory RuhlNitin BorkarShailendra JainVasantha ErraguntlaMichael KonowMichael RiepenMatthias GriesGuido DroegeTor Lund-LarsenSebastian SteiblShekhar BorkarVivek K. DeRob F. Van der WijngaartPublished in: IEEE J. Solid State Circuits (2011)
Keyphrases
- message passing
- power reduction
- power consumption
- silicon on insulator
- ibm power processor
- low power
- multithreading
- belief propagation
- power dissipation
- high speed
- power saving
- power management
- chip design
- distributed systems
- single chip
- cmos technology
- nm technology
- probabilistic inference
- shared memory
- energy efficiency
- instruction set
- approximate inference
- factor graphs
- error resilience
- inference in graphical models
- sum product algorithm
- markov random field
- distributed memory
- distributed shared memory
- low cost
- graphical models
- graph cuts
- message passing interface
- parallel processing
- sum product
- junction tree
- computer vision
- parallel algorithm
- stereo matching
- image registration
- preprocessing
- reinforcement learning
- three dimensional