Satish Yada

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 5

Top Topics

Low Power Consumption

Cmos Technology

Multi Robot Cooperative

Top Venues

Publications

Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. ISCAS (2022)
Srivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Dileep Kurian, Erika Ramirez Lozano, Satish Yada, Saransh Chhabra, Kamakhya Prasad Sahu, Paolo A. Aseron, Ronald Kalim, Anuradha Srinivasan, Tanay Karnik
Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. ISQED (2022)
Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, R. Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, C. Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits (2020)
Vinayak Honkote, Dileep Kurian, Sriram Muthukumar, Dibyendu Ghosh, Satish Yada, Kartik Jain, Bradley Jackson, Ilya Klotchkov, Mallikarjuna Rao Nimmagadda, Shreela Dattawadkar, Pranjali Deshmukh, Ankit Gupta, Jaykant Timbadiya, Ravi Pali, Karthik Narayanan, Saksham Soni, Saransh Chhabra, Praveen Dhama, N. Sreenivasulu, Jisna Kollikunnel, Sureshbabu Kadavakollu, Vijay Deepak Sivaraj, Paolo A. Aseron, Leonid Azarenkov, Nancy Robinson, Arun Radhakrishnan, Mikhail J. Moiseev, Ganeshram Nandakumar, Akhila Madhukumar, Roman Popov, Kamakhya P. Sahu, Ramesh Peguvandla, Alberto Del Rio Ruiz, Mukesh Bhartiya, Anuradha Srinivasan, Vivek De
A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. ISSCC (2019)
Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC (2018)
Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. VLSI Design (2012)
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar
An IA-32 processor with a wide voltage operating range in 32nm CMOS. Hot Chips Symposium (2012)
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC (2012)
Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC (2010)
Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji
Modified Stability Checking for On-line Error Detection. VLSI Design (2007)