Rajaraman Ramanarayanan

Publication Activity (10 Years)

Years Active: 2003-2013
Publications (10 Years): 0

Top Topics

Sparse Matrices

Top Venues

IEEE Symposium on Computer Arithmetic

Publications

Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla
Split-Path Fused Floating Point Multiply Accumulate (FPMAC). IEEE Symposium on Computer Arithmetic (2013)
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar
An IA-32 processor with a wide voltage operating range in 32nm CMOS. Hot Chips Symposium (2012)
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC (2012)
Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy
18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. ESSCIRC (2010)
Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC (2010)
Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Secur. Comput. 6 (3) (2009)
Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. VLSI Design (2008)
Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. VLSI Design (2007)
Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, Rajaraman Ramanarayanan, Balaji Vaidyanathan
A Process Scheduler-Based Approach to NoC Power Management. VLSI Design (2007)
Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
The Effect of Threshold Voltages on the Soft Error Rate. ISQED (2004)
Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
Effect of Power Optimizations on Soft Error Rate. VLSI-SoC (Selected Papers) (2003)