Bharadwaj S. Amrutur

Publication Activity (10 Years)

Years Active: 1992-2020
Publications (10 Years): 7

Top Topics

Shandong Province

Safety Analysis

Top Venues

IEEE Trans. Biomed. Circuits Syst.

Publications

Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur
A RISC-V ISA Compatible Processor IP. VDAT (2020)
Srikrishna Acharya, Bharadwaj S. Amrutur, Yogesh Simmhan, Aditya Gopalan, Parimal Parag, Himanshu Tyagi
CORNET: A Co-Simulation Middleware for Robot Networks. COMSNETS (2020)
Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur
A Custom Designed RISC-V ISA Compatible Processor for SoC. VDAT (2017)
V. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur
Improved Methods for Accurate Safety Analysis of Real-Life Systems. ATS (2015)
Sagar Venkatesh Gubbi, Bharadwaj S. Amrutur
Adaptive Pulse Width Control and Sampling for Low Power Pulse Oximetry. IEEE Trans. Biomed. Circuits Syst. 9 (2) (2015)
Prachet Verma, Akshay Kumar, Nihesh Rathod, Pratik Jain, Mallikarjun Sunkenapally, Renu Subramanian, Bharadwaj S. Amrutur, M. S. Mohan Kumar, Rajesh Sundaresan
Towards an IoT based water management system for a campus. ISC2 (2015)
R. R. Manikandan, Bharadwaj S. Amrutur
A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs. Microelectron. J. 46 (6) (2015)
R. R. Manikandan, Venkata Narayana Rao Vanukuru, Anjan Chakravorty, Bharadwaj S. Amrutur
Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors. VDAT (2014)
Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. J. Electron. Test. 26 (3) (2010)
Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur
In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits. ISLPED (2010)
Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. VLSI Design (2008)
S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. VLSI Design (2008)
Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat
Optimal power and noise allocation for analog and digital sections of a low power radio receiver. ISLPED (2008)
M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji
False Error Study of On-line Soft Error Detection Mechanisms. IOLTS (2008)
Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji
Modified Stability Checking for On-line Error Detection. VLSI Design (2007)
Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan
A scalable low power issue queue for large instruction window processors. ICS (2006)
Bharadwaj S. Amrutur, Mark A. Horowitz
Fast low-power decoders for RAMs. IEEE J. Solid State Circuits 36 (10) (2001)
Bharadwaj S. Amrutur, Mark A. Horowitz
Speed and power scaling of SRAM's. IEEE J. Solid State Circuits 35 (2) (2000)
Bharadwaj S. Amrutur, Mark A. Horowitz
A replica technique for wordline and sense control in low-power SRAM's. IEEE J. Solid State Circuits 33 (8) (1998)
Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, Shin Mitara
Low-power SRAM design using half-swing pulse-mode techniques. IEEE J. Solid State Circuits 33 (11) (1998)
Bharadwaj S. Amrutur, Rajeev Joshi, Narendra K. Karmarkar
A projective geometry architecture for scientific computation. ASAP (1992)