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Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique.
Rakesh Gnana David Jeyasingh
Navakanta Bhat
Bharadwaj S. Amrutur
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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logic circuits
low power
functional decomposition
computer vision
case study
design process
real time
user interface
gate array