Kuruvilla Varghese

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 17

Top Topics

Convolutional Neural Network

Mass Spectrometry Data

High Throughput

Top Venues

Publications

Ajay S, Praveen V. S, Kuruvilla Varghese
An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment. APCCAS (2023)
Shrutheesh Raman Iyer, Kuruvilla Varghese, Raghu Krishnapuram, Panini Bhamidipati
Deep-Feature-Based Visual Odometry for Autonomous Emergency Parking. AIR (2023)
Sadhu Sai Ram, Kuruvilla Varghese
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. APCCAS (2023)
Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese
Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core. VLSID (2023)
A. BhanuPrasad, Kuruvilla Varghese
High Throughput Hardware Acceleration for Image Generation using HLS. APCCAS (2023)
Dola Ram, Suraj Panwar, Kuruvilla Varghese
Hardware Accelerator for Capsule Network based Reinforcement Learning. VLSID (2022)
V. Naveen Chander, Kuruvilla Varghese
A Soft RISC-V Vector Processor for Edge-AI. VLSID (2022)
Ramakant Joshi, Kuruvilla Varghese
High-Level Synthesis of Geant4 Particle Transport Application for FPGA. DSD (2022)
Srikrishna Acharya, S. Sadgun S. Devanahalli, Alok Rawat, Kuruvilla Varghese, Pratik Sharma, Bharadwaj Amrutur, Ashish Joglekar, Raghu Krishnapuram, Yogesh Simmhan, Himanshu Tyagi
Network Emulation For Tele-driving Application Development. COMSNETS (2021)
T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese
Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. DSD (2020)
Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur
A RISC-V ISA Compatible Processor IP. VDAT (2020)
Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese
FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training. DSD (2018)
Nimish Shah, Paragkumar Chaudhari, Kuruvilla Varghese
Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 29 (12) (2018)
Arnab Dey, Sebin Jose, Kuruvilla Varghese, Shayan Garani Srinivasa
A high-throughput clock-less architecture for soft-output Viterbi detection. MWSCAS (2017)
Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur
A Custom Designed RISC-V ISA Compatible Processor for SoC. VDAT (2017)
Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa
A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. VLSI Design (2016)
Sriram Venkateshan, Alap Patel, Kuruvilla Varghese
Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Karthikeyan Pandiyarajan, Srijith Haridas, Kuruvilla Varghese
Transparent FPGA based device for SQL DDoS mitigation. FPT (2013)
Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese
HD Resolution Intra Prediction Architecture for H.264 Decoder. VLSI Design (2012)
Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese
A scalable network port scan detection system on FPGA. FPT (2011)
Vrishali Vijay Nimbalkar, Kuruvilla Varghese
In-channel Flow Control Scheme for Network-on-Chip. DSD (2010)
Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese
Area optimized H.264 Intra prediction architecture for 1080p HD resolution. ASAP (2010)
Gandhi Arpit, Raghavendra Adiga, Kuruvilla Varghese
Space Efficient Diagonal Linear Space Sequence Alignment. BIBE (2010)
G. Vikas, Joy Kuri, Kuruvilla Varghese
Power optimal Network-on-Chip interconnect design. SoCC (2009)
J. Divyasree, H. Rajashekar, Kuruvilla Varghese
Dynamically reconfigurable regular expression matching architecture. ASAP (2008)
Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese
A Scalable High Throughput Firewall in FPGA. FCCM (2008)