Tejasvi Anand

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 30

Top Topics

Analog To Digital Converter

Error Correction

Metal Oxide Semiconductor

Top Venues

IEEE J. Solid State Circuits

Publications

Andrew Ensinger, Ramin Javadi, Xiaohui Lin, Bella Bose, Tejasvi Anand
Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE). ISCAS (2024)
Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. IEEE J. Solid State Circuits 59 (8) (2024)
Mohamed Megahed, Tejasvi Anand
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS. IEEE J. Solid State Circuits 58 (5) (2023)
Vladimir Veselý, Calvin Yoji Lee, Tejasvi Anand, Un-Ku Moon
PLL-SAR: A New High-Speed Analog to Digital Converter Architecture. MWSCAS (2023)
Xiaohui Lin, Mohamed Megahed, Tejasvi Anand
A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. VLSI Technology and Circuits (2022)
Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. IEEE J. Solid State Circuits 57 (5) (2022)
Soumya Bose, Tejasvi Anand, Matthew L. Johnston
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting. IEEE J. Solid State Circuits 56 (6) (2021)
Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. VLSI Circuits (2021)
Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand
A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. VLSI Circuits (2021)
Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. IEEE J. Solid State Circuits 55 (7) (2020)
Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon
Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. IEEE J. Solid State Circuits 55 (2) (2020)
Yusang Chun, Tejasvi Anand
An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit. IEEE J. Solid State Circuits 55 (3) (2020)
Tejasvi Anand
A Stochastic Wireline Communication System. MWSCAS (2019)
Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand
A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2019)
Yusang Chun, Tejasvi Anand
A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS. CICC (2019)
Soumya Bose, Tejasvi Anand, Matthew L. Johnston
A 3.5mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting. CICC (2019)
Yusang Chun, Ashwin Ramachandran, Tejasvi Anand
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS. ESSCIRC (2019)
Soumya Bose, Tejasvi Anand, Matthew L. Johnston
Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator. IEEE J. Solid State Circuits 54 (10) (2019)
Mohamed Megahed, Y. Ramadass, Tejasvi Anand
A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm. CICC (2019)
Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Bodhisatwa Sadhu, Tejasvi Anand, Scott K. Reynolds
A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation. IEEE J. Solid State Circuits 53 (9) (2018)
Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. IEEE J. Solid State Circuits 53 (3) (2018)
Soumya Bose, Tejasvi Anand, Matthew L. Johnston
Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump. CICC (2018)
Ashwin Ramachandran, Tejasvi Anand
A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS. ISSCC (2018)
Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon
A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. CICC (2017)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52 (9) (2017)
Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS. ISSCC (2017)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52 (5) (2017)
Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu
A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity. IEEE J. Solid State Circuits 51 (11) (2016)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 51 (2) (2016)
Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits 50 (4) (2015)
Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. IEEE J. Solid State Circuits 50 (12) (2015)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50 (4) (2015)
Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits 50 (12) (2015)
Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits 50 (3) (2015)
Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC (2015)
Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu
A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS. VLSIC (2015)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC (2015)
Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. ISSCC (2015)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC (2014)
Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits 49 (10) (2014)
Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. IEEE J. Solid State Circuits 49 (10) (2014)
Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC (2014)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC (2014)
Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu
order CT-ΔΣ modulator using VCO-based integrators. VLSIC (2014)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC (2014)
Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC (2013)
Vikram Chaturvedi, Tejasvi Anand, Bharadwaj Amrutur
An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Kaushik Ghosal, Tejasvi Anand, Vikram Chaturvedi, Bharadwaj Amrutur
A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications. ICECS (2012)
Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese
A scalable network port scan detection system on FPGA. FPT (2011)