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A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS.
Mohamed Megahed
Tejasvi Anand
Published in:
IEEE J. Solid State Circuits (2023)
Keyphrases
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nm technology
cmos technology
management system
analog vlsi
high speed
software architecture
power consumption
low power
network architecture
energy minimization
circuit design
computational complexity
energy efficiency
image segmentation
markov random field
power reduction
low cost