José E. Schutt-Ainé

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 9

Top Topics

Electrical Energy

Hardware Implementation

Pipeline Architecture

Random Access Memory

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Tuomin Tao, Hanzhi Ma, Da Li, Yan Li, Shurun Tan, En-Xiao Liu, José E. Schutt-Ainé, Er-Ping Li
Modeling and Analysis of Spike Signal Sequence for Memristor Crossbar Array in Neuromorphic Chips. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (6) (2023)
Tuomin Tao, Da Li, Hanzhi Ma, Yan Li, Shurun Tan, En-Xiao Liu, José E. Schutt-Ainé, Er-Ping Li
A new pre-conditioned STDP rule and its hardware implementation in neuromorphic crossbar array. Neurocomputing 557 (2023)
Wei Chun Chin, Andrei Pashkovich, José E. Schutt-Ainé, Nur Syazreen Ahmad, Patrick Goh
Thin-Film Transistor Simulations With the Voltage-In-Current Latency Insertion Method. IEEE Access 9 (2021)
Xinying Wang, Thong Nguyen, José E. Schutt-Ainé
PAM-4 Behavioral Modeling using Machine Learning via Laguerre-Volterra Expansion. LASCAS (2020)
Da-Wei Wang, Wenchao Chen, Wen-Sheng Zhao, Guo-Dong Zhu, Kai Kang, Pingqi Gao, José E. Schutt-Ainé, Wen-Yan Yin
Fully Coupled Electrothermal Simulation of Large RRAM Arrays in the "Thermal-House". IEEE Access 7 (2019)
Da-Wei Wang, Wenchao Chen, Wen-Sheng Zhao, Guo-Dong Zhu, Zhen-Guo Zhao, José E. Schutt-Ainé, Wen-Yan Yin
An Improved Algorithm for Drift Diffusion Transport and Its Application on Large Scale Parallel Simulation of Resistive Random Access Memory Arrays. IEEE Access 7 (2019)
José E. Schutt-Ainé, Patrick Goh
LIM Algorithms for MOSFET Models. LASCAS (2019)
Thong Nguyen, Tianjian Lu, Ken Wu, José E. Schutt-Ainé
Fast Transient Simulation of High-Speed Channels Using Recurrent Neural Network. CoRR (2019)
Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. IEEE J. Solid State Circuits 53 (3) (2018)
José E. Schutt-Ainé, Patrick Goh
Phase-locked loop simulations using the latency insertion method. LASCAS (2013)
Josh G. Nickel, José E. Schutt-Ainé
Topological realizability conditions and their interpretation for admittance matrices of an MTL system with mode delays. J. Frankl. Inst. 344 (6) (2007)
José E. Schutt-Ainé, Sung-Mo Kang
Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends). Proc. IEEE 89 (4) (2001)
José E. Schutt-Ainé
High-frequency characterization of twisted-pair cables. IEEE Trans. Commun. 49 (4) (2001)
José E. Schutt-Ainé, Sung-Mo Kang
Scanning the issue interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling). Proc. IEEE 89 (5) (2001)
Wendemagegnehu T. Beyene, José E. Schutt-Ainé
Transient analysis of diode switching circuits using asymptotic waveform evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (12) (1997)
José E. Schutt-Ainé, Kyung-soo Oh
Modeling Interconnections with Nonlinear Discontinuities. ISCAS (1993)
Dimitri Kuznetsov, José E. Schutt-Ainé
Difference Model Approach for the Transient Simulation of Transmission Lines. ISCAS (1993)