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A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS.
Ashwin Ramachandran
Tejasvi Anand
Published in:
ISSCC (2018)
Keyphrases
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high speed
power consumption
pulse width modulation
low power
cmos technology
parallel processing