Brian Young

Publication Activity (10 Years)

Years Active: 1996-2017
Publications (10 Years): 1

Top Topics

Noise Sensitivity

Top Venues

IEEE J. Solid State Circuits

Publications

Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52 (9) (2017)
Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. VLSIC (2015)
Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49 (4) (2014)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC (2014)
Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. IEEE J. Solid State Circuits 49 (5) (2014)
Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits 49 (10) (2014)
Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. IEEE J. Solid State Circuits 49 (4) (2014)
Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu
order CT-ΔΣ modulator using VCO-based integrators. VLSIC (2014)
Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC (2013)
Pavan Annangi, Navneeth Subramanian, Satish C. Govind, Gokul Swamy, Brian Young
Automated posteriorwall thickness measurement from B-mode ultrasound. ISBI (2013)
Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE J. Solid State Circuits 48 (6) (2013)
Sri-Kaushik Pavani, Navneeth Subramanian, Mithun Das Gupta, Pavan Annangi, Satish C. Govind, Brian Young
Quality Metric for Parasternal Long Axis B-Mode Echocardiograms. MICCAI (2) (2012)
Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. ISSCC (2012)
Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC (2012)
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC (2012)
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits 47 (12) (2012)
Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC (2011)
Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC (2011)
Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. IEEE J. Solid State Circuits 46 (12) (2011)
Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. IEEE J. Solid State Circuits 46 (12) (2011)
Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. IEEE J. Solid State Circuits 46 (8) (2011)
Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. CICC (2010)
Adam L. Meyers, Ruth Reeves, Catherine Macleod, Rachel Szekely, Veronika Zielinska, Brian Young, Ralph Grishman
The NomBank Project: An Interim Report. FCP@NAACL-HLT (2004)
Adam L. Meyers, Ruth Reeves, Catherine Macleod, Rachel Szekely, Veronika Zielinska, Brian Young, Ralph Grishman
Annotating Noun Argument Structure for NomBank. LREC (2004)
Adam L. Meyers, Ruth Reeves, Catherine Macleod, Rachel Szekely, Veronika Zielinska, Brian Young
The Cross-Breeding of Dictionaries. LREC (2004)
Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw
On-chip inductance modeling and analysis. DAC (2000)
Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
Model and analysis for combined package and on-chip power grid simulation. ISLPED (2000)
Winfred Arthur, Brian Young, Jeffrey A. Jordan, Wayne L. Shebilske
Effectiveness of Individual and Dyadic Training Protocols: The Influence of Trainee Interaction Anxiety. Hum. Factors 38 (1) (1996)