Woo-Seok Choi

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 46

Top Topics

Metal Oxide Semiconductor

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Hyeri Roh, Jinsu Yeo, Yeongil Ko, Gu-Yeon Wei, David Brooks, Woo-Seok Choi
Flash: A Hybrid Private Inference Protocol for Deep CNNs with High Accuracy and Low Latency on CPU. CoRR (2024)
Woo-Seok Choi, Kyu-Min Shim, Kyung-Ho Chong, Jun-Eon An, Cheon-Joong Kim, Byung-Yoon Park
Sagnac Effect Compensations and Locked States in a Ring Laser Gyroscope. Sensors 23 (3) (2023)
Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi
A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM. ESSCIRC (2023)
Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. A-SSCC (2023)
Jeongeun Song, Sunyoung Lee, Minseok Shin, Ohjun Kwon, Hansang Kim, Yujin Park, Gyubeom Hwang, Hyekyoung Jung, Hoesam Jeong, Changrock Song, Woo-Seok Choi
A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors. ISOCC (2023)
Ju-Yeon Lee, Woo-Seok Choi, Sang-Hyun Choi
Verification and performance comparison of CNN-based algorithms for two-step helmet-wearing detection. Expert Syst. Appl. 225 (2023)
Kahyun Kim, Daeho Yun, Kyungmin Baek, Woo-Seok Choi, Deog-Kyoon Jeong
A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. ISCAS (2023)
Taehoon Kim, Yoona Lee, Woo-Seok Choi
Fast Performance Evaluation Methodology for High-speed Memory Interfaces. DATE (2023)
Hyeri Roh, Woo-Seok Choi
A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Jia Park, Woo-Seok Choi
An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism. ISOCC (2023)
Hyeri Roh, Woo-Seok Choi
Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference. CoRR (2023)
Taehoon Kim, Woo-Seok Choi
Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function. ISOCC (2023)
Kwang-Hoon Lee, Jung-Hun Park, Yongjae Lee, Yeonggeun Song, Seungha Roh, Minkyo Shim, Yoonho Song, Woosong Jung, Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. IEEE Trans. Circuits Syst. II Express Briefs 70 (11) (2023)
Jiwon Shin, Woo-Seok Choi
Phase Noise Analysis for Stochastically Injected Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 70 (8) (2023)
Hyeri Roh, Woo-Seok Choi
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis. ISOCC (2023)
Jihee Kim, Woo-Seok Choi
A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method. ISOCC (2023)
Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. VLSI Technology and Circuits (2022)
Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits 57 (6) (2022)
Daeho Yun, Eonhui Lee, Woosong Jung, Kahyun Kim, Kyung-Min Beak, Jihee Kim, Hyun Bae Lee, Byeongseon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Hanseok Kim, Woo-Seok Choi
Improving Spiking Neural Network Accuracy Using Time-based Neurons. CoRR (2022)
Joonghyun Song, Jiwon Shirn, Hanseok Kim, Woo-Seok Choi
Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. AICAS (2022)
Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. IEEE J. Solid State Circuits 57 (7) (2022)
Jia Park, Woo-Seok Choi
Impact of Oscillator Phase Noise on Time-Domain SNN Performance. ISOCC (2022)
Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Honggyoo Ahn, Joonghyun Song, Woo-Seok Choi
Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter. ISOCC (2022)
Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi
Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. CoRR (2022)
Hanseok Kim, Woo-Seok Choi
Improving Spiking Neural Network Accuracy Using Time-based Neurons. ISCAS (2022)
Joonghyun Song, Woo-Seok Choi
A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion. ISOCC (2022)
Hyunjun Park, Woo-Seok Choi
Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit. ISOCC (2022)
Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Han-Gon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC (2021)
Dongwook Kim, Mostafa Gamal Ahmed, Woo-Seok Choi, Ahmed Elkholy, Pavan Kumar Hanumolu
A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 55 (8) (2020)
Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu
0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. IEEE J. Solid State Circuits 54 (8) (2019)
Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu
A 15-Gb/s Sub-Baud-Rate Digital CDR. IEEE J. Solid State Circuits 54 (3) (2019)
Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar
Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA (2018)
Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. IEEE J. Solid State Circuits 53 (3) (2018)
Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. IEEE J. Solid State Circuits 53 (3) (2018)
Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu
A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. CICC (2018)
Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu
A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. CICC (2018)
Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. CICC (2017)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52 (9) (2017)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52 (5) (2017)
Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC (2017)
Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC (2017)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC (2016)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 51 (2) (2016)
Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits 50 (4) (2015)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50 (4) (2015)
Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. ISSCC (2015)
Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits 50 (3) (2015)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC (2015)
Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49 (4) (2014)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC (2014)
Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC (2014)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC (2014)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC (2014)
Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46 (11) (2011)