C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS.
Junheng Zhu
Woo-Seok Choi
Pavan Kumar Hanumolu
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
</>
clock frequency
cmos technology
power consumption
high speed
nm technology
low power
mixed signal
power dissipation
low voltage
duty cycle
parallel processing
vlsi circuits
low cost
image sensor
neural network
development environment
high end
high frequency
fpga device
signal processing
digital libraries