Kwangho Lee

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 29

Top Topics

Cmos Technology

Graph Cut Segmentation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Kwangho Lee, Patrick Kwon, Myung-Ki Lee, Namhyuk Ahn, Junsoo Lee
LPMM: Intuitive Pose Control for Neural Talking-Head Model via Landmark-Parameter Morphable Model. CoRR (2023)
Byungjun Kim, Patrick Kwon, Kwangho Lee, Myunggi Lee, Sookwan Han, Daesik Kim, Hanbyul Joo
Chupa: Carving 3D Clothed Humans from Skinned Shape Priors using 2D Diffusion Probabilistic Models. CoRR (2023)
Byungjun Kim, Patrick Kwon, Kwangho Lee, Myunggi Lee, Sookwan Han, Daesik Kim, Hanbyul Joo
Chupa: Carving 3D Clothed Humans from Skinned Shape Priors using 2D Diffusion Probabilistic Models. ICCV (2023)
Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. IEEE J. Solid State Circuits 58 (5) (2023)
Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. IEEE J. Solid State Circuits 57 (10) (2022)
Seungha Roh, Kwangho Lee, Minkyo Shim, Moon-Chul Choi, Deog-Kyoon Jeong
A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Seungkwon Kim, Chaeheon Gwak, Dohyun Kim, Kwangho Lee, Jihye Back, Namhyuk Ahn, Daesik Kim
Cross-Domain Style Mixing for Face Cartoonization. CoRR (2022)
Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. A-SSCC (2021)
Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. A-SSCC (2021)
Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Jungseung Lee, Huijin Park, Kwangho Lee
Profiling Based I/O Optimization on the CE Devices. ICCE (2021)
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56 (5) (2021)
Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. A-SSCC (2021)
Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. IEEE J. Solid State Circuits 55 (8) (2020)
Moon-Chul Choi, Han-Gon Ko, Jonghyun Oh, Hye-Yoon Joo, Kwangho Lee, Deog-Kyoon Jeong
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. VLSI Circuits (2020)
Woosong Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, Deog-Kyoon Jeong
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface. ISOCC (2020)
Kwangho Lee, Joonho Kong, Young Geun Kim, Sung Woo Chung
Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing. Microprocess. Microsystems 71 (2019)
Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. VLSI Circuits (2019)
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits (2019)
Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54 (10) (2019)
Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Jinhyung Lee, Kwanseo Park, Kwangho Lee, Deog-Kyoon Jeong
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)
Mi Jin Lee, Kwangho Lee
The effect of contents on sixth graders' understanding about the height of triangles. Int. J. Knowl. Learn. 12 (4) (2018)
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC (2018)
Joonho Kong, Kwangho Lee
A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs. IEICE Electron. Express 14 (11) (2017)
Jungkyu Park, Kwangho Lee
Using board games to improve mathematical creativity. Int. J. Knowl. Learn. 12 (1) (2017)
Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)