Sang-Hyeok Chu

Publication Activity (10 Years)

Years Active: 2014-2020
Publications (10 Years): 5

Top Topics

Video Watermarking

False Alarm Probability

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. ISSCC (2020)
Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. BCICTS (2018)
Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
Bias. IEEE J. Solid State Circuits 51 (10) (2016)
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC (2015)
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. IEEE Trans. Circuits Syst. II Express Briefs (9) (2015)
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50 (11) (2015)
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. VLSIC (2015)
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC (2015)
Taeho Kim, Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog-Kyoon Jeong
A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs (5) (2014)
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC (2014)