Taeik Kim

Publication Activity (10 Years)

Years Active: 2003-2021
Publications (10 Years): 9

Top Topics

Cmos Technology

Fuzzy Connectedness

Noise Cancellation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jens Anders, Taeik Kim, David T. Blaauw
Session 5 Overview: Analog Interfaces Analog Subcommittee. ISSCC (2021)
Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Xiaohua Huang, Kunnong Zeng, Yuguang Liu, Woogeun Rhee, Taeik Kim, Zhihua Wang
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL. CICC (2019)
Man-Kay Law, Taeik Kim, Kofi A. A. Makinwa
Session 19 overview: Sensors and interfaces: Analog subcommittee. ISSCC (2018)
Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. BCICTS (2018)
Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko
fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. ISSCC (2018)
Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung Jong Ko, SeongHwan Cho
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique. IEEE J. Solid State Circuits 52 (11) (2017)
Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. ISSCC (2016)
Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. ISSCC (2015)
Yudong Zhang, Woogeun Rhee, Taeik Kim, Hojin Park, Zhihua Wang
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park
-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. ISSCC (2015)
Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee
A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS. CICC (2015)
Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. ISSCC (2015)
Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park
9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. CICC (2014)
Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park
3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. ISSCC (2014)
Sung-Jin Kim, Taeik Kim, Hojin Park
A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology. VLSIC (2014)
Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC (2013)
Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park
5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. ISSCC (2013)
Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park
2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. ISSCC (2012)
Taeik Kim, David J. Allstot
A tunable transmission line phase shifter (TTPS). ISCAS (1) (2004)
Taeik Kim, Xiaoyong Li, David J. Allstot
Compact model generation for on-chip transmission lines. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2004)
Taeik Kim, Xiaoyong Li, David J. Allstot
Accurate compact model extraction for on-chip coplanar waveguides. ISCAS (4) (2003)
Srinivas Kodali, Taeik Kim, David J. Allstot
On-chip inductor structures: a comparative study. ISCAS (1) (2003)