14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
Hyojun KimJinwoo SangHyunik KimYoungwoo JoTaeik KimHojin ParkSeongHwan ChoPublished in: ISSCC (2015)
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