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5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.

Tae-Kwang JangNan XingFrank LiuJungeun ShinHyungreal RyuJihyun F. KimTaeik KimJaejin ParkHojin Park
Published in: ISSCC (2013)
Keyphrases
  • phase locked loop
  • high voltage
  • single phase
  • data conversion
  • training phase
  • high speed
  • multipath
  • multiresolution