Jaejin Park

Publication Activity (10 Years)

Years Active: 1994-2017
Publications (10 Years): 2

Top Topics

Noise Cancellation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Vadim Ivanov, Jaejin Park
Session 12 overview: Efficient Power Conversion. ISSCC (2016)
Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park
3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. ISSCC (2014)
Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. IEEE J. Solid State Circuits 49 (3) (2014)
Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim
Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. ICCAD (2013)
Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC (2013)
Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park
5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. ISSCC (2013)
Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park
2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. ISSCC (2012)
Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. ISSCC (2012)
Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. A-SSCC (2011)
Jongsun Park, Jaejin Park, Suwang Jang, Seryun Kim, Sunghyung Kong, Jaeyoung Choi, Kyohun Ahn, Juhyeon Kim, Seungmin Lee, Sunggon Kim, Bongsoo Park, Kyongyong Jung, Soonok Kim, Seogchan Kang, Yong-Hwan Lee
FTFD: an informatics pipeline supporting phylogenomic analysis of fungal transcription factors. Bioinform. 24 (7) (2008)
Jongsun Park, Bongsoo Park, Kyongyong Jung, Suwang Jang, Kwangyul Yu, Jaeyoung Choi, Sunghyung Kong, Jaejin Park, Seryun Kim, Hyojeong Kim, Soonok Kim, Jihyun F. Kim, Jaime E. Blair, Kwangwon Lee, Seogchan Kang, Yong-Hwan Lee
CFGP: a web-based, comparative fungal genomics platform. Nucleic Acids Res. 36 (Database-Issue) (2008)
Jaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR. CICC (2007)
Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue
A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. ISCAS (2) (2005)
Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue
A low-power, 20-Gb/s continuous-time adaptive passive equalizer. ISCAS (2) (2005)
Jaejin Park, Ho-Jin Park, Jae-Whui Kim, Sangnam Seo, Philip Chung
A 1 mW 10-bit 500KSPS SAR A/D converter. ISCAS (2000)
Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song
A 5-MHz IF digital FM demodulator. IEEE J. Solid State Circuits 34 (1) (1999)
Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim
A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. IEEE J. Solid State Circuits 30 (8) (1995)
Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim
A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. ISCAS (1994)