Login / Signup
Jenlung Liu
Publication Activity (10 Years)
Years Active: 2011-2014
Publications (10 Years): 0
Top Topics
Noise Cancellation
Logic Circuits
Random Number Generator
Cmos Image Sensor
Top Venues
ISSCC
</>
Publications
</>
Jenlung Liu
,
Tae-Kwang Jang
,
Yonghee Lee
,
Jungeun Shin
,
Seunghoon Lee
,
Taeik Kim
,
Jaejin Park
,
Hojin Park
3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.
ISSCC
(2014)
Jong-Phil Hong
,
Sung-Jin Kim
,
Jenlung Liu
,
Nan Xing
,
Tae-Kwang Jang
,
Jaejin Park
,
Jihyun F. Kim
,
Taeik Kim
,
Hojin Park
2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.
ISSCC
(2012)
Jenlung Liu
,
Sehyung Jeon
,
Tae-Kwang Jang
,
Dohyung Kim
,
Jihyun F. Kim
,
Jaejin Park
,
Hojin Park
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS.
A-SSCC
(2011)