2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.
Jong-Phil HongSung-Jin KimJenlung LiuNan XingTae-Kwang JangJaejin ParkJihyun F. KimTaeik KimHojin ParkPublished in: ISSCC (2012)
Keyphrases
- low power
- power consumption
- mixed signal
- low cost
- high speed
- wireless transmission
- vlsi circuits
- single chip
- high power
- vlsi architecture
- low power consumption
- digital signal processing
- power reduction
- random number generator
- logic circuits
- image encryption
- cmos technology
- delay insensitive
- image sensor
- ultra low power
- circuit design
- cmos image sensor