Login / Signup
3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.
Wooseok Kim
Jaejin Park
Jihyun F. Kim
Taeik Kim
Hojin Park
Deog-Kyoon Jeong
Published in:
ISSCC (2013)
Keyphrases
</>
power consumption
high speed
wide range
low power
gray level
clock frequency
fpga device
three dimensional
multiscale
video sequences
hd video