A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology.
Sung-Jin KimTaeik KimHojin ParkPublished in: VLSIC (2014)
Keyphrases
- cmos technology
- low power
- power dissipation
- power consumption
- low cost
- high speed
- spl times
- low voltage
- single chip
- digital signal processing
- silicon on insulator
- mixed signal
- image sensor
- hidden markov models
- real time
- network on chip
- packet loss
- power management
- parallel processing
- finite state machines
- image processing
- cmos image sensor