Min-Seong Choo

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 20

Top Topics

Cmos Technology

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo
Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application. ICEIC (2024)
Seung-Mo Jin, Shin-Uk Kang, Min-Seong Choo
Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks. ICEIC (2024)
Dong-Hoe Heo, Tae-Hyeon Kim, Kwang-Ho Lee, Min-Seong Choo
An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery. ICEIC (2024)
Dongjun Lee, Gijin Park, Jaeduk Han, Min-Seong Choo
An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies. IEEE Access 11 (2023)
InWoo Jang, Min-Seong Choo
Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter. ICEIC (2023)
Shin-Uk Kang, Jin-Woo Han, Min-Seong Choo
Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application. ICEIC (2023)
Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC (2022)
Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56 (8) (2021)
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56 (5) (2021)
Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits (2019)
Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54 (10) (2019)
Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong
Controller and 80ns Recovery Time. ISSCC (2019)
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC (2018)
Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC (2017)
Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong
A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS (2016)
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC (2015)