6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.
Byoung-Joo YooDong-Hyuk LimHyonguk PangJune-Hee LeeSeung-Yeob BaekNaxin KimDong-Ho ChoiYoung-Ho ChoiHyeyeon YangTaehun YoonSang-Hyeok ChuKangjik KimWoochul JungBong-Kyu KimJaechol LeeGunil KangSang-Hune ParkMichael ChoiJongshin ShinPublished in: ISSCC (2020)
Keyphrases
- low power
- high speed
- power consumption
- digital signal processing
- cmos technology
- single chip
- wireless transmission
- data acquisition
- ultra low power
- low cost
- low power consumption
- high power
- vlsi architecture
- power reduction
- nm technology
- real time
- power saving
- hardware implementation
- power dissipation
- logic circuits
- mixed signal
- signal processing
- vlsi circuits