An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
Kwangho LeeHyojun KimWoosong JungJinhyung LeeHaram JuKwanseo ParkOok KimDeog-Kyoon JeongPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2021)
Keyphrases
- low power
- high speed
- cmos technology
- power consumption
- low cost
- nm technology
- single chip
- decision feedback
- logic circuits
- vlsi circuits
- vlsi architecture
- mixed signal
- low voltage
- digital signal processing
- low power consumption
- delay insensitive
- real time
- image sensor
- fading channels
- silicon on insulator
- gate array
- ultra low power
- power reduction
- imaging systems
- single input single output