Rajesh Inti

Publication Activity (10 Years)

Years Active: 2010-2022
Publications (10 Years): 4

Top Topics

Noise Sensitivity

Top Venues

IEEE J. Solid State Circuits

Publications

Mozhgan Mansuri, Rajesh Inti, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi
A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits 57 (3) (2022)
Rajesh Inti, Mozhgan Mansuri, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi
A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS. CICC (2021)
Sudip Shekhar, Rajesh Inti, James E. Jaussi, Tzu-Chien Hsueh, Bryan Casper
A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR. IEEE J. Solid State Circuits 54 (6) (2019)
Rajesh Inti, Mozhgan Mansuri, Joe Kennedy, Hariprasath Venkatram, Chun-Ming Hsu, Aaron Martin, James E. Jaussi, Bryan Casper
A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS. VLSI Circuits (2018)
Sudip Shekhar, Rajesh Inti, James E. Jaussi, Tzu-Chien Hsueh, Bryan Casper
A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR. VLSIC (2015)
Rajesh Inti, Sudip Shekhar, Ganesh Balamurugan, James E. Jaussi, Clark Roberts, Tzu-Chien Hsueh, Bryan Casper
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS. VLSIC (2015)
Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49 (4) (2014)
Tawfiq Musah, James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Gokce Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. IEEE J. Solid State Circuits 49 (12) (2014)
James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Tawfiq Musah, Gökçe Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS. ISSCC (2014)
Tzu-Chien Hsueh, Ganesh Balamurugan, James E. Jaussi, Sami Hyvonen, Joseph T. Kennedy, Gökçe Keskin, Tawfiq Musah, Sudip Shekhar, Rajesh Inti, Shreyas Sen, Mozhgan Mansuri, Clark Roberts, Bryan Casper
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS. ISSCC (2014)
Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE J. Solid State Circuits 48 (6) (2013)
Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. VLSIC (2012)
Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC (2012)
Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Peter Buchmann, Pier Andrea Francese, Thomas Morf
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC (2012)
Qadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. VLSIC (2012)
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC (2012)
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits 47 (12) (2012)
Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC (2011)
Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu
Digital clock and data recovery circuit design: Challenges and tradeoffs. CICC (2011)
Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC (2011)
Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. IEEE J. Solid State Circuits 46 (12) (2011)
Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC (2011)
Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. IEEE J. Solid State Circuits 46 (12) (2011)
Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. IEEE J. Solid State Circuits 46 (12) (2011)
Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. IEEE J. Solid State Circuits 46 (8) (2011)
Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC (2011)
Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu
A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. CICC (2010)