Naga Sasidhar

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Stochastic Optimization

Capacity Expansion

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Naga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un-Ku Moon
Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. IEEE Trans. Circuits Syst. II Express Briefs (9) (2012)
Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. IEEE J. Solid State Circuits 46 (12) (2011)
Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC (2011)
Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. IEEE J. Solid State Circuits 44 (9) (2009)
Venkata Srinivas, Shanthi Pavan, Ashish Lachhwani, Naga Sasidhar
A Distortion Compensating Flash Analog-to-Digital Conversion Technique. IEEE J. Solid State Circuits 41 (9) (2006)