Shanthi Pavan

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 58

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

ISCAS

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Shanthi Pavan
Systematic Development of CMOS PTAT Circuits. ISCAS (2024)
Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining. IEEE J. Solid State Circuits 59 (1) (2024)
Javad Gorji, Shanthi Pavan, José M. de la Rosa
On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (3) (2024)
Shanthi Pavan, Gabor C. Temes
Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (9) (2023)
Javad Gorji, Shanthi Pavan, José M. de la Rosa
Bandpass $\Delta \Sigma$ Modulators with FIR Feedback. ISCAS (2023)
Chaitanya Kumar, Shanthi Pavan
Power-Noise Trade-Offs in Continuous-Time Pipelined ADCs and Active Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Nishanth Basavaraj, Shanthi Pavan
Digital Reconstruction in Continuous-Time Pipelined Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Alok Baluni, Shanthi Pavan
A 13.5 mW Decimator for a 20 MHz bandwidth CTΔΣ Modulator using poly-phase decomposition techniques. ICECS (2023)
Shanthi Pavan, Gabor C. Temes
Reciprocity and Inter-Reciprocity: A Tutorial - Part II: Linear Periodically Time-Varying Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (9) (2023)
Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan
Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs. IEEE J. Solid State Circuits 57 (11) (2022)
Shanthi Pavan
Systematic Development of CMOS Fixed-Transconductance Bias Circuits. IEEE Trans. Circuits Syst. II Express Briefs 69 (5) (2022)
Chaitanya Kumar, Saravana Manivannan, Shanthi Pavan
Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC. ISCAS (2022)
Nishanth Basavaraj, Saravana Manivannan, Shanthi Pavan
Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs 69 (10) (2022)
Saravana Manivannan, Shanthi Pavan
Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Raviteja Theertham, Shanthi Pavan
Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
-order Vector-Quantizer DEM. CICC (2022)
Shanthi Pavan, Saravana Manivannan
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Shanthi Pavan, Tanmay Halder, Anand Kannan
Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Alok Baluni, Shanthi Pavan
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback. IEEE J. Solid State Circuits 56 (3) (2021)
Shanthi Pavan, Hajime Shibata
Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68 (3) (2021)
Udita Mukherjee, Tanmay Halder, Anand Kannan, Sovan Ghosh, Shanthi Pavan
A 28.5µW All-Analog Voice-Activity Detector. ISCAS (2021)
Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan
Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density. IEEE J. Solid State Circuits 55 (9) (2020)
Raviteja Theertham, Shanthi Pavan
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. ISCAS (2020)
Saravana Manivannan, Shanthi Pavan
Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering. IEEE Trans. Circuits Syst. (11) (2020)
Sujith Billa, Suhas Dixit, Shanthi Pavan
Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator. IEEE J. Solid State Circuits 55 (10) (2020)
Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya Bhat, Shanthi Pavan
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC (2020)
Alok Baluni, Shanthi Pavan
A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC. CICC (2020)
Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting. IEEE J. Solid State Circuits 54 (9) (2019)
Shanthi Pavan
An Alternative Approach to Bode's Noise Theorem. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
Shanthi Pavan, Raviteja Theertham
Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Raviteja Theertham, Shanthi Pavan
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Sujith Billa, Suhas Dixit, Shanthi Pavan
A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth. A-SSCC (2019)
Saravana Manivannan, Shanthi Pavan
Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities. ISCAS (2019)
Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan
A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. VLSI Circuits (2019)
Kishalay Datta, Vinod Menezes, Shanthi Pavan
Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Shanthi Pavan
Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters. ISCAS (2019)
Shanthi Pavan, Eric A. M. Klumperink
Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2018)
Shanthi Pavan
Practical design and simulation techniques for continuous-time ΔΣ converters. CICC (2018)
Saravana Manivannan, Shanthi Pavan
Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. ESSCIRC (2018)
Shanthi Pavan, Siddharth Baskaran
What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator? ISCAS (2018)
Ankesh Jain, Shanthi Pavan
Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Shanthi Pavan
Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters. CICC (2018)
Shanthi Pavan
Improved Chopping in Continuous-Time Delta-Sigma Converters Using FIR Feedback and N-Path Techniques. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Saravana Manivannan, Shanthi Pavan
A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR. CICC (2018)
Shanthi Pavan, Eric A. M. Klumperink
Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Neha Sinha, Mansour Rachid, Shanthi Pavan, Sudhakar Pamarti
Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components. IEEE J. Solid State Circuits 52 (8) (2017)
Shanthi Pavan
Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. IEEE J. Solid State Circuits 52 (12) (2017)
Shanthi Pavan, Eric A. M. Klumperink
Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2017)
Sujith Billa, Amrith Sukumaran, Shanthi Pavan
Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. IEEE J. Solid State Circuits 52 (9) (2017)
Shanthi Pavan
On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters. ISCAS (2017)
Ankesh Jain, Shanthi Pavan
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. VLSI Circuits (2016)
Amrith Sukumaran, Shanthi Pavan
Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs. IEEE J. Solid State Circuits 51 (7) (2016)
Shanthi Pavan, Nagendra Krishnapura
Demystifying Time Varying Circuits and Systems. VLSI Design (2016)
Sujith Billa, Amrith Sukumaran, Shanthi Pavan
15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. ISSCC (2016)
Shanthi Pavan
Continuous-time ΔΣ modulators with dual switched capacitor resistor DACs. ISCAS (2016)
Kamlesh Singh, Shanthi Pavan
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition. VLSI Design (2016)
José M. de la Rosa, Richard Schreier, Kong-Pang Pun, Shanthi Pavan
Next-Generation Delta-Sigma Converters: Trends and Perspectives. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (4) (2015)
Amrith Sukumaran, Shanthi Pavan
A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC. ESSCIRC (2015)
Shanthi Pavan
Outgoing Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
José M. de la Rosa, Richard Schreier, Kong-Pang Pun, Shanthi Pavan
Guest Editorial: Next-Generation Delta-Sigma Converters. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (4) (2015)
Sandeep Krishnan, Shanthi Pavan
A 10 Gbps eye opening monitor in 65nm CMOS. ISCAS (2015)
Naga Rajesh, Shanthi Pavan
Programmable analog pulse shaping for ultra-wideband applications. ISCAS (2015)
Shanthi Pavan
Incoming Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Naga Rajesh, Shanthi Pavan
Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming. IEEE J. Solid State Circuits 49 (8) (2014)
Shanthi Pavan, Radha S. Rajan
Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs (9) (2014)
Radha S. Rajan, Shanthi Pavan
Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering. IEEE J. Solid State Circuits 49 (10) (2014)
Shanthi Pavan, Radha S. Rajan
Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs. IEEE Trans. Circuits Syst. II Express Briefs (9) (2014)
Radha S. Rajan, Shanthi Pavan
-order active filter and VGA achieving 82dB DR in 2MHz BW. ISSCC (2014)
Shanthi Pavan
Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
Amrith Sukumaran, Shanthi Pavan
Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback. IEEE J. Solid State Circuits 49 (11) (2014)
Shanthi Pavan
Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator. ISCAS (2014)
Ankesh Jain, Shanthi Pavan
Characterization Techniques for High Speed Oversampled Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
Yong Lian, Sergios Theodoridis, George Yuan, Shanthi Pavan
Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013). IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
Shanthi Pavan
A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time ΔΣ Modulator. IEEE Trans. Circuits Syst. II Express Briefs (2) (2013)
Ankesh Jain, Shanthi Pavan
Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface. ISCAS (2013)
Shanthi Pavan, John W. M. Rogers, Vikas Chandra
Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012). IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2013)
Shanthi Pavan, Wouter A. Serdijn, Henry Shu-Hung Chung, Ming-Der Shieh, Young Hwan Kim
Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012). IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2013)
Naga Rajesh, Shanthi Pavan
A lumped component programmable delay element for Ultra-Wideband beamforming. CICC (2013)
Timir Nandi, Karthikeya Boominathan, Shanthi Pavan
Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC. IEEE J. Solid State Circuits 48 (8) (2013)
Pradeep Shettigar, Shanthi Pavan
Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs. IEEE J. Solid State Circuits 47 (12) (2012)
Timir Nandi, Karthikeya Boominathan, Shanthi Pavan
A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC. CICC (2012)
Radha S. Rajan, Shanthi Pavan
Device Noise in Continuous-Time Oversampling Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2012)
Radha S. Rajan, Shanthi Pavan
Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs. ISCAS (2012)
Chip-Hong Chang, Howard C. Luong, Shanthi Pavan
Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011). IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Pradeep Shettigar, Shanthi Pavan
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. ISSCC (2012)
Un-Ku Moon, Shanthi Pavan
Little-known features of well-known creatures. ISSCC (2012)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania
A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. IEEE J. Solid State Circuits 47 (8) (2012)
Ankesh Jain, Muthusubramaniam Venkatesan, Shanthi Pavan
Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique. IEEE J. Solid State Circuits 47 (7) (2012)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera
A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. CICC (2011)
Ankesh Jain, Muthusubramanian Venkateswaran, Shanthi Pavan
A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range. ESSCIRC (2011)
Shanthi Pavan
Alias Rejection of Continuous-Time DeltaSigma Modulators With Switched-Capacitor Feedback DACs. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2011)
Shanthi Pavan
The inconvenient truth about alias rejection in continuous time ΔΣ converters. ISCAS (2011)
Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar
Active-RC Filters Using the Gm-Assisted OTA-RC Technique. IEEE J. Solid State Circuits 46 (7) (2011)
Shanthi Pavan
On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs. IEEE Trans. Circuits Syst. II Express Briefs (5) (2011)
Shanthi Pavan
Systematic Design Centering of Continuous Time Oversampling Converters. IEEE Trans. Circuits Syst. II Express Briefs (3) (2010)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)
Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar
Low distortion active filters using the Gm-assisted OTA-RC technique. ESSCIRC (2010)
Shanthi Pavan, Prabu Sankar
Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique. IEEE J. Solid State Circuits 45 (7) (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Shanthi Pavan