Nagendra Krishnapura

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 36

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Nagendra Krishnapura
Analysis of Signal Transmission through Time-Varying Inductively Coupled Links. ISCAS (2024)
Aditya Narayanan, Nagendra Krishnapura
Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs. ICECS (2023)
Sumit Kumar, Nagendra Krishnapura
Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis. APCCAS (2023)
Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura
Bandpass Filter and Oscillator ICs with THD ppd for Testing High-Resolution ADCs. ISSCC (2023)
Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, Nagendra Krishnapura
A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur. APCCAS (2023)
Abhishek Bhat, Nagendra Krishnapura
for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
R. S. Ashwin Kumar, Nagendra Krishnapura
Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
R. S. Ashwin Kumar, Nagendra Krishnapura, Paramita Banerjee
Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier. IEEE J. Solid State Circuits 57 (11) (2022)
Yun Chiu, Man-Kay Law, Nagendra Krishnapura, Jason T. Stauth, Jeffrey S. Walling
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 56 (12) (2021)
Chithra, Aditya Narayanan, R. S. Ashwin Kumar, Nagendra Krishnapura
Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Imon Mondal, Nagendra Krishnapura
Effects of AC Response Imperfections in True-Time-Delay Lines. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura
A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process. ISCAS (2020)
Chithra, Nagendra Krishnapura
A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2020)
Purnendu Bhattaru, Nagendra Krishnapura
A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems. VLSI Design (2020)
R. S. Ashwin Kumar, Nagendra Krishnapura
Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset. IEEE Trans. Circuits Syst. (11) (2020)
M. V. Praveen, Nagendra Krishnapura
High Linearity Transmit Power Mixers Using Baseband Current Feedback. IEEE J. Solid State Circuits 55 (2) (2020)
Vipul Bajaj, Anand Kannan, Minkle E. Paul, Nagendra Krishnapura
Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters. ISCAS (2020)
R. S. Ashwin Kumar, Nagendra Krishnapura
A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter. ESSCIRC (2019)
Abhishek Bhat, Nagendra Krishnapura
On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Chithra, Nagendra Krishnapura
Static Phase Offset Reduction Technique for Delay Locked Loops. ISCAS (2019)
Sangeeta Kumar, Rajashekar Goroju, Dileep Kumar Bhat, K. S. Rakshitdatta, Nagendra Krishnapura
Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Abhishek Bhat, Nagendra Krishnapura
A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios. ISSCC (2019)
Nagendra Krishnapura, Anoop Narayan Bhat, Subhashish Mukherjee, Kumar Anurag Shrivastava, Madhulatha Bonu
Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
R. S. Ashwin Kumar, Debasish Behera, Nagendra Krishnapura
Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Abhishek Bhat, Nagendra Krishnapura
Phase Noise Quadrature LC VCOs. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Imon Mondal, Nagendra Krishnapura
Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
M. V. Praveen, Nagendra Krishnapura
An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters. ISCAS (2018)
Imon Mondal, Nagendra Krishnapura
Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load. ISCAS (2018)
Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Venugopal Gopinathan, Ganesan Thiagarajan, Abhijit Patki, Jhankar Malakar, Nagendra Krishnapura
25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS. ISSCC (2017)
Nagendra Krishnapura, Ken Suyama
Session 12-Analog techniques I. CICC (2017)
Sumit Kumar, Nagendra Krishnapura
Optimum scaling of stages in a frequency divider chain for best jitter FoM. ISCAS (2017)
Imon Mondal, Nagendra Krishnapura
A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13µm CMOS. IEEE J. Solid State Circuits 52 (8) (2017)
Ashwin Kumar Siva Kumar, Debasish Behera, Nagendra Krishnapura
A Low Power Multi-channel Input Delta-Sigma ADC without Reset. VLSI Design (2017)
Shanthi Pavan, Nagendra Krishnapura
Demystifying Time Varying Circuits and Systems. VLSI Design (2016)
Abhishek Bhat, Nagendra Krishnapura
A tail-resonance calibration technique for wide tuning range LC VCOs. ISCAS (2016)
K. S. Rakshitdatta, Yujendra Mitikiri, Nagendra Krishnapura
A 12.5 mW, 11.1 nV√Hz, -115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 µm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (5) (2016)
Imon Mondal, Nagendra Krishnapura
Gain enhanced high frequency OTA with on-chip tuned negative conductance load. ISCAS (2015)
Imon Mondal, Nagendra Krishnapura
Accurate Constant Transconductance Generation without Off-Chip Components. VLSI Design (2015)
K. S. Rakshitdatta, Nagendra Krishnapura
On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback. VLSI Design (2015)
Nagendra Krishnapura, K. S. Rakshitdatta
A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Debasish Behera, Nagendra Krishnapura
A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter. ESSCIRC (2014)
Nagendra Krishnapura
Tutorial T6A: Pedagogy of Negative Feedback Circuits. VLSI Design (2014)
Nagendra Krishnapura, K. S. Rakshitdatta
A model-agnostic technique for simulating per-element distortion contributions. CICC (2013)
Nagendra Krishnapura
Introducing negative feedback with an integrator as the central element. ISCAS (2012)
Nagendra Krishnapura
Synthesis based introduction to opamps and phase locked loops. ISCAS (2012)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania
A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. IEEE J. Solid State Circuits 47 (8) (2012)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera
A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. CICC (2011)
Nagendra Krishnapura
Electronic time stretching for fast digitization. ISCAS (2011)
Nagendra Krishnapura, Abhishek Agrawal, Sameer Singh
A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Chembiyan Thambidurai, Nagendra Krishnapura
On Pulse Position Modulation and Its Application to PLLs for Spur Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2011)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)
Nagendra Krishnapura
Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters. ISCAS (2010)
Shankar Parameswaran, Nagendra Krishnapura
A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator. ISCAS (2010)
Chembiyan Thambidurai, Nagendra Krishnapura
Spur reduction in wideband PLLs by random positioning of charge pump current pulses. ISCAS (2010)
Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura
A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. VLSI Design (2009)
Nagendra Krishnapura, Shanthi Pavan
Negative Feedback System and Circuit Design. VLSI Design (2009)
Shanthi Pavan, Nagendra Krishnapura
Oversampling Analog-to-Digital Converter Design. VLSI Design (2008)
Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar
A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. IEEE J. Solid State Circuits 43 (2) (2008)
Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar
A 90μW 15-bit ΔΣ ADC for digital audio. ESSCIRC (2007)
Shanthi Pavan, Nagendra Krishnapura
Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs (4) (2007)
Nagendra Krishnapura, Yannis P. Tsividis
Micropower low-voltage analog filter in a digital CMOS process. IEEE J. Solid State Circuits 38 (6) (2003)
Nagendra Krishnapura, Yannis P. Tsividis
Noise and power reduction in filters through the use of adjustable biasing. IEEE J. Solid State Circuits 36 (12) (2001)
Nagendra Krishnapura, Peter R. Kinget
A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS. IEEE J. Solid State Circuits 35 (7) (2000)