A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS.
Nagendra KrishnapuraPeter R. KingetPublished in: IEEE J. Solid State Circuits (2000)
Keyphrases
- high speed
- low cost
- single chip
- low power
- power consumption
- floating gate
- cmos image sensor
- signal processor
- analog vlsi
- delay insensitive
- real time
- frequency band
- power supply
- cmos technology
- low voltage
- intel xeon
- circuit design
- general purpose
- video sequences
- random access memory
- focal plane
- vlsi circuits
- dual band
- image sensor
- dielectric constant
- hd video